RISC-V Multistage Pipelined CPU
Designed and implemented a 5-stage pipelined processor in SystemVerilog to support the RISC-V RV32I ISA. Implemented a branch prediction module for conditionals and function calls/returns with a BTB. Measured processor performance with matrix multiplication benchmarks.[link]
This 5-stage pipelined CPU supports the RV32I RISC-V instruction set architecture (ISA). The processor also includes RAW hazard detection, branch prediction, and a direct-mapped cache (see MEM stage). The main bottlenecks are the cache miss rate and the BTB miss rate, both of which necessitate processor stalls (incurring instruction delays).
Tests included:
- Mixed program (programs with poor functional locality)
- Matrix multiplication (no optimization)
- Matrix multiplication (-O3 compiler optimization)
