Arden Diakhate-Palme

Developed a networking stack in C for an STM32 using LoRa transceivers. Implemented link-state routing and the spanning-tree protocol. Minimized node power-consumption with smart scheduling, low-power processor modes, and by modifying neighbor-discovery algorithms.

Designed and implemented a 5-stage pipelined processor in SystemVerilog to support the RISC-V RV32I ISA. Implemented a branch prediction module for conditionals and function calls/returns with a BTB. Measured processor performance with matrix multiplication benchmarks.

Implemented on an ARM Cortex M processor in C using rate monotonic scheduling, immediate ceiling priority protocol, and memory protection.